1. Field of the Invention
The present invention relates to insulated gate devices such as insulated gate transistors (IGT's) and metal-oxide-semiconductor field-effect-transistors (MOSFET's) which have lateral surface channels and more specifically to a method for reducing the width of such channels.
2. Description of the Related Art
FIG. 1(a) is a cross sectional view of a typical power MOSFET 1 which is fabricated on a semiconductor substrate 2 and connected in series to an external load R.sub.LOAD and a power supply +HV. When the MOSFET 1 is switched to the ON state, a conductive series path forms internally between a source terminal S and a drain terminal D. It is desirable to minimize the total resistance of this internal conductive path, hereinafter referred to as the total on resistance R.sub.DSon, such that maximum power will be delivered to the external load R.sub.LOAD. When the MOSFET 1 is switched to the OFF state, it is desirable to form a nonconductive reverse bias area between the D and S terminals that is able to withstand relatively large voltages without breaking down. Furthermore, activation of an inherent parasitic transistor formed by the source, channel and drain regions of the device (described below) is to be avoided for proper operation of the MOSFET 1.
A compromise has usually been struck between the above mentioned objectives when devices such as the MOSFET 1 of FIG. 1(a) are designed. Realization of both a high voltage block in the nonconducting OFF state and low internal resistance during the conducting ON state is often difficult because of a common pinching mechanism that affects both parameters in a counteracting manner. The pinching mechanism is believed to occur generally within a vertical portion 31 of a drain region 30 disposed under an insulated polysilicon gate 20 of the MOSFET 1. The pinching mechanism adversely affects the conductivity of the vertical drain portion 31, primarily between opposed knee segments, 14d and 14d', of a pair of wells 14 and 14' by depleting charge carriers from that area during the ON state. When the MOSFET is in the OFF state however, the same pinching mechanism enhances the MOSFET's ability to withstand relatively large voltages without breaking down.
In one prior device, a doping agent was implanted at the top surface 32d of a drain epitaxial region 32 to establish a relatively high doping concentration N.sub.I + in the vertical drain portion 31 of the MOSFET. A relatively low doping concentration N- existed in remaining portions of the drain epitaxial region 32, below the vertical portion 31. The surface implant concentration N.sub.I + of the single doping agent was adjusted to set the on resistance R.sub.DSon and the maximum blocking voltage V.sub.DSmax of the MOSFET through counteracting aspects of the pinching mechanism.
Aspects of the pinching mechanism that contribute to the on resistance R.sub.DSon of the illustrated MOSFET 1 may be better understood by referring also to an enlarged view of a portion of the MOSFET 1 shown in FIG. 1(b) and to the equivalent circuit of FIG. 2(a). When a gate voltage V.sub.G, applied to the polysilicon gate 20 exceeds a predetermined threshold voltage of the MOSFET, charge carrier inversion occurs within a relatively small inversion depth a (usually less than one micron) just below the top surface 2a of the substrate 2. This creates an n-channel 15 in a p-type double-diffused well 14 of the MOSFET 1.
A channel region 14a projects to the substrate surface 2a from the P-well 14. The well 14 includes a shallow region 14b, contiguous with and extending vertically downward from the channel region 14a, and a surface contact region 14c (FIG. 1(a)), overlying a deeper portion 14e of the double diffused P-well. A silicon dioxide insulating layer 22 separates the polysilicon gate 20 from the top surface 2a of the channel region 14a.
When the n-channel 15 (FIG. 1(b)) is induced by an appropriate gate voltage VG, it acts as an n-type conductive layer that communicates laterally between a heavily doped n-type source region 12 (N+) and the top of the vertical drain portion 31 (N.sub.I +) (FIG. 1(a)). The n-channel 15 completes a conductive series path between the S and D terminals, allowing an electron current I.sub.DSe to flow laterally from a source contact layer 10, through the source region 12 (N+), to a top layer 32a of the drain epitaxial region 32. The current I.sub.DSe continues downwardly through a middle layer 32b and bottom layer 32c of the drain epitaxial region 32 to exit the MOSFET through a heavily doped bulk region 34 (N+) and a metal drain contact layer 36.
As the electron current I.sub.DSe flows through the described path, it encounters several resistances including a channel resistance R.sub.CH (FIG. 2(a)), a pinch off resistance R.sub.JFET, and an epitaxial resistance R.sub.EPX. In general, the first two resistances are believed to result from narrow constrictions in lateral and vertical portions of the described conductive path. The induced n-channel 15 in the lateral portion of the conductive path, for example, is typically less than one micron deep and often forms to a depth of less than 0.1 micron. The channel resistance R.sub.CH is determined primarily by the inversion depth a of the induced n-channel 15 and the lateral width L.sub.CH of the channel region 14a.
The pinch off resistance R.sub.JFET results from a depletion zone constriction in the middle portion 32b of the drain epitaxial region 32 which occurs at a pinching depth b (see FIG. 1(b)) between closely spaced opposing knee segments, 14d and 14d' of the shallow regions 14b and 14b' of one or more double diffused P-wells 14, 14' that are formed around the vertical drain portion 31 (FIG. 1(a)) during fabrication. Shallow regions 14b and 14b' are separated from the adjacent vertical drain portion 31 by a PN junction which is generally reverse biased such that a charge carrier depletion zone 35 (dotted area) grows outwardly from the PN junction into the middle layer 32b of the vertical drain portion 31 as the voltage V.sub.DS, applied between the D and S terminals, increases. As the depletion zone 35 expands into region 32, it reduces the conductive cross-sectional area of region 32, particularly in the vertical drain region between the opposed knee segments, 14d and 14d'. This constriction of the conductive cross-sectional area, commonly known as pinching creates the R.sub.JFET resistance to curent flow.
The third resistance, R.sub.EXP results from the light doping (N-) in the relatively wide bottom layer 32c of the epitaxial region 32. Light doping of the bottom layer 32c is believed to cause an enlargement in the width of the depletion zone 35 surrounding the PN junction between the P-wells 14, 14' and the bottom layer 32c. This enlargement of the depletion zone minimizes lectric field intensity within the semiconductor material of the substrate 2 surrounding the PN junction and helps prevent avalanche breakdown when the MOSFET 1 is switched to the OFF state.
The total on resistance R.sub.DSon of the MOSFET is determined in major by the sum of R.sub.CH, R.sub.JFET, and R.sub.EPX. These internal resistances consume power and generate undesirable heat inside the MOSFET. R.sub.DSon is preferably made as low as possible to minimize undesirable heat generation within the MOSFET and improve the energy efficiency of the device.
U.S. Pat. No. 4,593,302 to Lidow et al. describes a method for reducing pinch off resistance R.sub.JFET by ion implantation of a single doping agent (phosphorous) along the substrate surface 2a overlying the vertical drain portion 31 of the drain epitaxial region 32 prior to high temperature processing. During high temperature processing, the implanted doping agent diffuses down into the middle layer 32b of the epitaxial region 32 (N-) to increase the doping concentration of that region from N- to a predetermined higher level N.sub.I +. This implanted doping concentration, N.sub.I +, is intended to reduce pinch off resistance R.sub.JFET in the middle layer 32b by slowing depletion zone growth between and beneath the opposed knee segments 14d and 14d' of the shallow regions 14b, 14b' of the P-wells 14, 14'.
While it is possible to reduce on resistance R.sub.DSon by increasing the concentration N.sub.I + of the doping implant described by Lidow et al., an increase of the doping concentration N.sub.I + at the depth of the middle layer 32b can unfortunately also reduce the maximum blocking voltage VDS.sub.max of the MOSFET 1. When the MOSFET 1 is turned off, a portion of the depletion zone 35 near the knee segment 14d of the shallow region 14b begins to grow from a conduction state boundary line 35a (FIG. 1(b)) toward a pinch off boundary line 35b. At the pinch off boundary line 35b, the depletion zone 35 merges with an opposed depletion zone boundary line 35b' growing from the opposed knee segment 14d' of an opposing P-well 14' (FIG. 1(a)). This merger of the opposed depletion zone boundaries, commonly known as pinch off, creates a high resistance area that extends laterally across the vertical drain portion 31 and blocks relatively large voltages +HV, occurring within the bottom layer 32c of the drain epitaxial region from reaching weak portions of the PN junction near the substrate surface 2a. As a general rule, the upper vertical portions of the PN junction terminating at the substrate surface 2a are not able to withstand large voltages without breaking down when the MOSFET is turned off. However, if the shallow P-well regions 14b, 14b'are diffused to a sufficient depth D.sub.S (FIG. 1(a)), pinch off can be made to occur between opposed knee segments 14d, 14d' at a protective pinching depth b located beneath weak portions of the PN junction so as to protect the upper portions from exposure to large voltages. When choosing the dimensions of insulated gate devices such as the MOSFET 1, the p-well diffusion depth D.sub.s is often selected with this pinch off mechanism in mind. The design parameters required for such pinch off are well known in the field. These designs parameters are described for example, in the GE Handbook: Design Manual for Prediction of the Avalanche Breakdown Voltage of Silicon Semiconductor Devices, by Adler and Temple, incorporated herein by reference.
In addition to the creation of a merged depletion zone beneath weak upper layers of the vertical drain region during the OFF state of the MOSFET 1, the diffusion depth D.sub.S of the shallow regions 14b plays an important role in the ON state. An undesirable parasitic transistor (NPN), formed by the source region 12, well 14, and bottom layer 32c of the drain 30 can be activated when the MOSFET is in the ON state if the vertical distance D.sub.V (FIG. 1(a)) between the bottom of the source region 12 and the drain epitaxial region 32 is sufficiently narrow. Activation of this undesirable parasitic transistor is avoided among other ways, by diffusing the shallow regions 14b, 14b' to a preselected depth D.sub.S below the substrate surface 2a such that the vertical separation distance D.sub.V between the source and drain regions is sufficiently wide to prevent parasitic transistor turn on.
Referring still to FIG. 1(a), it will be appreciated by those skilled in the art that concomitant to any diffusion in the vertical direction to a preselected depth D.sub.S, the doping agent used for forming the shallow region 14b diffuses laterally under the polysilicon gate 20 by a proportional lateral distance D.sub.L measured from the edge 20e of the gate layer. This lateral diffusion distance D.sub.L ultimately determines the width L.sub.CH of the channel region 14a and establishes therefrom, the channel resistance R.sub.CH of the MOSFET 1. A trade off is often necessary between diffusion to a desired shallow well depth D.sub.S and minimization of the channel resistance which contributes to the total on resistance R.sub.DSon of the device (FIG. 2(a)).
In the Lidow fabrication method (U.S. Pat. No. 4,593,302), the total on resistance R.sub.DSon of an MOSFET is minimized by increasing the implant doping concentration N.sub.I + so as to reduce the pinch off resistance R.sub.JFET. But N.sub.I + cannot be increased without limit. Assuming that various factors such as the distance between opposed knee segments 14d, 14d' of the P-wells are predetermined, and the depth D.sub.s of the shallow region 14b is preselected to prevent parasitic transistor turn on, any adjustment of the implant doping concentration N.sub.I + is necessarily confined to levels below a maximum doping level N.sub.k at the pinching depth b if catastrophic avalanche breakdown is to be avoided. As noted earlier, the depletion zone 35 tends to be wider in lightly doped regions like the bottom layer 32c (N-) of the drain epitaxial region 32. There are fewer charge carriers in lightly doped regions so depletion occurs at a faster rate when a reverse bias voltage is applied across the PN junction. N.sub.k is a hypothetical doping level above which the depletion zone 35 (FIG. 1(b)) grows too slowly and therefore fails to reach the pinch off boundary line 35b before a critical electric field develops in weak regions above the protective pinching depth b, allowing the device to go into avalanche breakdown.
The relationship between the implant doping concentration N.sub.I + at the protective pinching depth b and premature breakdown at voltages below a desired maximum blocking voltage V.sub.DSmax is perhaps better explained by reference to a schematic diagram. FIG. 2 (b) is a simplified schematic diagram of the MOSFET 1 in its high voltage blocking mode. More heavily doped portions of the semiconductor material surrounding the reverse biased PN junction are not capable of withstanding the same reverse voltages which can be safely applied to the lighter doped regions (N-) because the depletion zone 35 does not expand as rapidly in the areas where charge carrier concentration is higher. Since the doping concentration N.sub.I + in the vertical drain portion 31 is the most heavily doped region adjacent to the PN junction of FIG. 2(b), the implant concentration just below the protective pincing depth b is in effect the weakest part of that PN junction. Consequently, any increase of the implant doping concentration N.sub.I + at the substrate surface increases the doping concentration just below the protective pinching depth b and weakens the PN junction's ability to withstand large reverse voltages V.sub.DSmax in the current blocking mode. Design flexibility for selecting the implant doping concentration N.sub.I + is therefore limited to a choice between reducing R.sub.DSon by increasing N.sub.I + or maximizing V.sub.DSmax by decreasing N.sub.I + for devices fabricated according to U.S. Pat. No. 4,593,302.